SEMICONDUCTOR CHIP PACKAGE AND METHOD OF FABRICATING THE SAME

摘要

A semiconductor chip package capable of improving reliability at a chip interconnection portion and improving reliability in a solder joint by reducing thermal and mechanical stresses at an external portion of the package including a solder ball land, and a method of fabricating the package are provided. The method of fabricating a semiconductor chip package includes providing a substrate; forming a first underfill on a first portion of the substrate; forming a second underfill at a chip interconnection portion of the substrate; and mounting a semiconductor chip on the chip interconnection portion using conductive bumps. In the method, the second underfill is formed of a material having a modulus higher than the first underfill.