发明名称 Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications
摘要 A substrate for multi-chip stacking and a multi-chip stack package utilizing the substrate and its applications are disclosed. The substrate comprises a first wire-bonding finger, a second wire-bonding finger, a trace configured for electrical transmission and a loop wiring on a same surface. The first wire-bonding finger and the second wire-bonding finger are adjacent each other and to a die-attaching area of the substrate. The loop wiring connects the first wire-bonding finger with the second wire-bonding finger in series and connected to the trace. The loop wiring can be selectively broken or not when at least two chips are stacked on the die-attaching area and electrically connected to the first and second wire-bonding fingers respectively. Accordingly, the chips can operate respectively and independently without mutual interference if one of the chips is fail. Moreover, there is merit to apply the multi-chip stack package utilizing the substrate because it can be repaired after molding and without removing any bonding wire during semiconductor packaging processes.
申请公布号 US2008265389(A1) 申请公布日期 2008.10.30
申请号 US20070790826 申请日期 2007.04.27
申请人 POWERTECH TECHNOLOGY INC. 发明人 HSU HUNG-HSIN;WU CHIH-WEI
分类号 H01L23/02 主分类号 H01L23/02
代理机构 代理人
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