| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a frame synchronizing circuit and a method that output input data of a plurality of systems by frame synchronization with minimum storage capacity of a buffer memory. <P>SOLUTION: The input data of the plurality of systems are written to a plurality of buffer memories 12 under the control of a WR counter 11 inputting frame synchronizing signals of the respective systems. A pulse extension unit 13 which inputs the count output of the WR counter 11 and the respective frame synchronizing signals inputs extended pulses having an arbitrary phase adjustment length to an adder 14 to find a maximum value and, and an RD synchronization timing generating unit 17 generates an RD synchronization timing signal with the count value of a frame counter 15 corresponding to the maximum value to control an RD counter 18, thereby reading frame-synchronized output data out of the buffer memories 12. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
