| 摘要 |
<p>Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on- insulator (SOI) wafer such that the insulator layer (202, 302) remains intact during subsequent deep trench etch processes and, optionally, such that the deep trench (250, 350) of the deep trench capacitor has different shapes and sizes at different depths. By forming the deep trench (250, 350) with different shapes and sizes at different depths the capacitance of the capacitor (210, 310) can be selectively varied and the resistance of the buried conductive strap (230, 330) which connects the capacitor (210, 310) to a transistor (220, 320) in a memory device can be reduced.</p> |
