发明名称 DEFECT MANAGEMENT FOR A SEMICONDUCTOR MEMORY SYSTEM
摘要 A method is provided for managing defects in a semiconductor memory system having a plurality of addressable locations. In the method, a first plurality of the addressable locations is allocated as in-use locations, and a second plurality of the addressable locations is allocated as spare locations. A plurality of sets of the in-use locations, wherein each of the sets is associated with a memory defect, is determined. At least one of the sets includes a different number of in-use locations than another of the sets. Each of the sets of the in-use locations is associated with at least one corresponding set of the spare locations. Each of a plurality of data requests that is associated with one of the sets of the in-use locations is directed to the at least one corresponding set of the spare locations.
申请公布号 US2008270675(A1) 申请公布日期 2008.10.30
申请号 US20070740052 申请日期 2007.04.25
申请人 NAGARAJ DHEEMANTH;THAYER LARRY J 发明人 NAGARAJ DHEEMANTH;THAYER LARRY J.
分类号 G06F12/00 主分类号 G06F12/00
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