发明名称 WAFER-LEVEL RELIABILITY YIELD ENHANCEMENT SYSTEM AND RELATED METHOD
摘要 A yield enhancement system has a fabrication line with semiconductor fabrication devices for fabricating a wafer, an inspection and measurement monitoring system coupled to the fabrication line for determining process data corresponding to semiconductor fabrication devices, and a post-process testing line coupled to the fabrication line for performing in-line wafer-level testing. The post-process testing line includes a wafer acceptance tester, a yield monitor coupled to the wafer acceptance tester, and a wafer level reliability tester coupled to the wafer acceptance tester for estimating a life span of a device on the wafer.
申请公布号 US2008270056(A1) 申请公布日期 2008.10.30
申请号 US20070740916 申请日期 2007.04.26
申请人 YANG YUN-CHI;LIN CHENG-LI;KAO CHIA-JEN;CHEN JU-PING;SU KUAN-CHENG 发明人 YANG YUN-CHI;LIN CHENG-LI;KAO CHIA-JEN;CHEN JU-PING;SU KUAN-CHENG
分类号 H01L21/66;G01N37/00 主分类号 H01L21/66
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