| 摘要 |
Provided are a system and method for timing improvements by dual output synchronizing buffer. The method comprises providing at least two outputs on a synchronizing first-in-first-out buffer ("FIFO") in a combinational logic circuit. The method further includes latching data into the FIFO. The method also includes alternating which of the two outputs by which the data is latched out of the FIFO, thereby extending timing in the combinational logic circuit.
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