| 摘要 |
<P>PROBLEM TO BE SOLVED: To stabilize the jitter resistance of a frequency tracking loop in a clock and data recovery circuit. <P>SOLUTION: A phase detector 210 compares a synchronous clock from a phase interpolator 270 with a phase of a serial data and outputs a phase error signal corresponding to a comparison result. A first integrator 230 integrates the phase error signal and obtains a phase correction control signal for tracking phase fluctuations. A second integrator 240 further integrates the phase correction control signal and obtains an up/down signal. A pattern generator 250 generates a frequency correction control signal for tracking frequency fluctuations of the serial data from the up/down signal. The product of the pattern length of the pattern generator 250 and counted width of the second integrator 240 becomes equal to or greater than the threshold of the magnitude, the larger the counted width of the first integrator is. <P>COPYRIGHT: (C)2009,JPO&INPIT |
