| 摘要 |
The field of the invention is that of transmission interfaces for synchronous digital input signals composed of bits transmitted in series at a frequency of transmission equal to a first integer multiple M of a first clock frequency. The interface according to the invention comprises at least one deserializer operating in over-sampling mode and supplying digital output samples of each bit in parallel. The output samples are transmitted at a second clock frequency, integer multiple N of a third frequency. The third frequency is substantially equal to the first frequency. Each sampled bit is substantially composed of N samples. The interface has an electronic device for frequency-locking the third frequency onto the first clock frequency. The device has means for counting the number of samples composing each sampled bit. The device also has incrementation-decrementation means for the third clock frequency configured in such a manner that the third clock frequency is increased when the number of samples is less than the integer multiple N and decreases when the number of samples is greater than N.
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