LIQUID CRYSTAL DISPLAY DRIVE CIRCUIT, LIQUID CRYSTAL DISPLAY DRIVE METHOD AND LIQUID CRYSTAL DISPLAY APPARATUS

摘要

A latch signal delay circuit (4) is a circuit that delays a latch signal (LS0) by times corresponding to the respective ones of source drivers (SD1-SD8) at clock (CLK) timings and that comprises shift registers. The latch signal delay circuit (4) outputs latch signals (LS1-LS8) to the respective source drivers (SD1-SD8).The output circuit (25) in each of the source drivers (SD1-SD8) inverts the polarity of data to a polarity indicated by an inputted polarity inversion signal at a timing of the rising edge of the respective one of the latch signals (LS1-LS8), and then outputs the resulting data. For this reason, when the latch signals (LS1-LS8) delay, deviation in polarity inversion timing occurs among the source drive outputs. Therefore, the energy caused by the current flowing in a source bus line at the polarity inversion timing is dispersed, so that the energy of noise is dispersed.