PROCESSOR SYSTEM, BUS CONTROLLING METHOD, AND SEMICONDUCTOR DEVICE

摘要

Provided is a simply structured multiprocessor system which equally distributes access performance for accessing a shared memory among plural master units accessing the shared memory. The multiprocessor system includes plural master units PU 0 and PU 1 each of which issues an access request for accessing the shared memory, a bus IF unit 4 - 10 which accesses a bus by a split transaction scheme and separately executes a request phase for accepting the access request; and a transfer phase for executing data transfer in response to the accepted access request. In the case where one of the master units consecutively issues plural access requests without an interval of a predetermined time period, the bus IF unit 4 - 10 restricts the number of consecutive transfer phase executions corresponding to the plural access requests to be not more than N.