Method for creating a layout, use of a transistor layout, and semiconductor circuit

摘要

The circuit has a matching structure with multiple transistors (M), where metallization levels with geometrically formed traces are formed directly above the transistors. Vias are provided in via levels that are formed between two of the metallization levels. Geometry of the traces above each transistor is formed substantially the same, within one and the same metallization level. The transistors of the matching structure are arranged adjacent to one another. The geometry of the traces within the metallization level has multiple strips parallel to one another. Independent claims are also included for the following: (1) a method for generating a layout of a semiconductor circuit having a matching structure (2) Use of a transistor layout of a matching structure in a layout generating method.