发明名称 Decoding apparatus with a plurality of memories for decoding of LDPC codes
摘要 In the present invention, there is provided a decoding apparatus for decoding low density parity check codes, including: a plurality of storage sections configured to store logarithmic likelihood ratios or logarithmic posteriori probability ratios for one codeword into addresses thereof which are independent of each other thereamong; and a readout section configured to simultaneously read out, from among the logarithmic likelihood ratios or logarithmic posteriori probability ratios for the one codeword stored in the storage sections, a plurality of ones of the logarithmic likelihood ratios or logarithmic posteriori probability ratios which correspond to non-zero value elements in a predetermined one row of the check matrix used in a coding process of the low density parity check codes.
申请公布号 EP1986329(A1) 申请公布日期 2008.10.29
申请号 EP20080007862 申请日期 2008.04.23
申请人 SONY CORPORATION 发明人 SHINAGAWA, MASASHI;YAMAGISHI, HIROYUKI;NODA, MAKOTO
分类号 H03M13/11 主分类号 H03M13/11
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