| 摘要 |
Disclosed is a digital circuit which comprises input signals A[n-1:0], SH[log<SUB>2</SUB>n-1:0], and DAT[n-1:0], a barrel shifter for outputting data B[n-1:0] obtained by shifting the signal DAT by the bits of the signal SH, a group G.P.SUM computation stage for dividing each of the digits of the input signals A and B into groups of m bits, and computing Gs, Ps, and addition results SUM 0 when carry inputs are high and addition results SUM 1 when the carry inputs are low, a carry computation circuit for computing a carry for each of the groups, and a SUM selection stage for selecting a SUM 0 or a SUM 1 computed for each of the groups according to each carry output by the carry computation circuit.
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