| 摘要 |
A method and apparatus are described for testing at least one critical data path in a design of a digital integrated circuit chip during a simulation of the design. A dedicated memory-bypass-enable signal is provided to a memory-bypass-logic circuit of the design during test modes of the simulation. Data content of a memory circuit within the critical data path is protected, using the dedicated memory-bypass-enable signal, during part of a path-delay test mode of the simulation. The memory circuit is also bypassed using the memory-bypass-enable signal during a memory-bypass test mode of the simulation.
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