发明名称 |
Reducing multiplexer circuitry for operand select logic associated with a processor |
摘要 |
Methods and apparatus are provided for reducing the amount of resources allocated for handling multiplexing in a processor. Characteristics associated with processing blocks are analyzed. Operand restrictions and register groups can be configured to allow the use of more resource efficient multiplexing circuitry in a processor.
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申请公布号 |
US7441105(B1) |
申请公布日期 |
2008.10.21 |
申请号 |
US20040870749 |
申请日期 |
2004.06.16 |
申请人 |
ALTERA CORPORATION |
发明人 |
METZGEN PAUL |
分类号 |
G06F7/38;G06F9/00;G06F9/44;G06F15/00 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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