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发明名称
积体电路结构及其制作方法
摘要
本发明揭示一种积体电路结构及其制法。此积体电路结构包括:一半导体基底;一介电层于该半导体基底上;一开口于介电层中;一导线于开口中;一金属合金层于该导线上;一第一金属矽化物层于该金属合金层上;以及,一第二金属矽化物层于第一金属矽化物层上。在上述中,第二金属矽化物层与第一金属矽化物层相异,且金属合金层、第一金属矽化物层、及第二金属矽化物层实质上垂直对准导线。
申请公布号
TW200841418
申请公布日期
2008.10.16
申请号
TW096139817
申请日期
2007.10.24
申请人
台湾积体电路制造股份有限公司
发明人
石健学;眭晓林
分类号
H01L21/768(2006.01)
主分类号
H01L21/768(2006.01)
代理机构
代理人
洪澄文;颜锦顺
主权项
地址
新竹市新竹科学工业园区力行六路8号
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