| 摘要 |
<p>A nonvolatile memory device and a method for manufacturing the same are provided to implement a uniform distribution and to reduce an SILC(Stress Induced Leakage Current) current by increasing an oxide valley on an upper interface of a floating gate. A tunnel dielectric(20) is formed on a semiconductor substrate(10). A first silicon layer(32) and second silicon layers(31,33) are laminated on the tunnel dielectric to form a floating gate. The second silicon layers have a grain size less than that of the first silicon layer. A dielectric is formed on the second silicon layer. A control gate is formed on the dielectric. The second silicon layer is an amorphous silicon layer. The second silicon layer is deposited under 600 °C. The second silicon layer has more small oxide valley than the first silicon layer. The second silicon layer is an undoped silicon layer. The amorphous silicon layer is deposited and a partial thickness of the amorphous silicon layer is crystallized with a poly silicon to form the first silicon layer.</p> |
