| 摘要 |
PROBLEM TO BE SOLVED: To provide a design method for a semiconductor integrated circuit, having more than two substrate potentials with the semiconductor integrated circuit being small in area, high in speed, and low in power consumption. SOLUTION: The design method comprises: a step L for preparing layout information to lay elements, forming a logical circuit out on a semiconductor substrate; a step P for preparing logical circuit information; a step a for classifying routes for propagation of a signal in a logic circuit, according to the logical circuit information; a step b for separating the logic circuits forming the routes classified in the classifying step a into the number of stages; a step c for classifying the elements, forming the logical circuit into the substrate potentials; and a step d for correcting the layout information so as to locate lager element at a position closer to a substrate contact. COPYRIGHT: (C)2009,JPO&INPIT
|
