| 摘要 |
PROBLEM TO BE SOLVED: To detect illegal access to a shared memory. SOLUTION: The multiprocessor system comprises a plurality of cache memories 21 provided in conformation to a plurality of processor cores 11 and including a tag storage part 22 storing valid information, update information and address information; a shared memory 14 shared by the plurality of processor cores 11; and an arbiter circuit 13 which adjusts access requests to the shared memory 14 from the plurality of processor cores 11, and transmits the adjusted access requests to the shared memory 14 and the plurality of cache memories 21. Each of the access requests includes an identification signal showing that data of a cache line is rewritten. Each of the plurality of cache memories 21 includes an illegality detection circuit 24 which compares information in the tag storage information 22 with the access request from the arbiter circuit 13 to detect illegal access. COPYRIGHT: (C)2009,JPO&INPIT
|
