发明名称 |
COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS |
摘要 |
A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip.
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申请公布号 |
US2008256405(A1) |
申请公布日期 |
2008.10.16 |
申请号 |
US20080143007 |
申请日期 |
2008.06.20 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
EUSTIS STEVEN M.;MONZEL JAMES A.;OAKLAND STEVEN F.;OUELLETTE MICHAEL R. |
分类号 |
G01R31/3185;G01R31/3187;G06F11/25 |
主分类号 |
G01R31/3185 |
代理机构 |
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地址 |
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