| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor device the flexibility of the layout of which can be assured by relaxing the density of first layer wiring, in which the parasitism resistor and the parasitism capacitance of the first layer wiring can be reduced, and which can be manufactured without any increase in the number of manufacturing steps, and its manufacturing method. <P>SOLUTION: There is provided the semiconductor device 10 in which a memory cell region and a peripheral circuit region are provided on a substrate. In the semiconductor device 10, assist wiring on the same layer as a landing pad 48 arranged for contact with a cell transistor on the bottom surface side of a capacitor of a memory cell region is provided on a peripheral circuit region or a border region of the memory cell region and the peripheral circuit region. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
