发明名称 MANUFACTURING METHOD FOR WIRING BOARD, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, AND WIRING BOARD
摘要 <P>PROBLEM TO BE SOLVED: To solve the problem that a crack is generated in an insulating layer surrounding the periphery of an electrode pad by a thermal stress. <P>SOLUTION: A semiconductor device 100 has a configuration flip-chip mounting a semiconductor chip 110 to a wiring board 120. The wiring board 120 has a multilayer structure laminating a plurality of wiring layers and a plurality of the insulating layers, and has the configuration laminating the insulating layers for a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128. A second electrode pad 132 is formed on a boundary surface between a first insulating layer 121 and a second insulating layer 123 in a width broader in the radial direction (the plane direction) than the outside diameter of a first electrode pad 130. Since there is the second electrode pad 132 formed in the width boarder than the first electrode pad 130 between the first electrode pad 130 and a via 134, the progressive direction of the thermal stress by a reflow treatment is interrupted and the thermal stress is absorbed in the direction along the boundary surface between the first insulating layer 121 and the second insulating layer 123. <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2008251702(A) 申请公布日期 2008.10.16
申请号 JP20070089019 申请日期 2007.03.29
申请人 SHINKO ELECTRIC IND CO LTD 发明人 KOBAYASHI KAZUHIRO
分类号 H01L21/60;H05K3/34;H05K3/38;H05K3/40 主分类号 H01L21/60
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