| 摘要 |
A Q enhancement circuit and method. In a most general embodiment, the inventive circuit is adapted for use with a component having a parasitic resistance R<SUB>3 </SUB>and a first resistance R<SUB>1 </SUB>disposed in series with the component and an arrangement for making the resistance a negative resistance. In the illustrative embodiment, first and second inductors constitute the components for which Q enhancement is effected. A resistance R<SUB>1 </SUB>is disposed in series with the first inductor and is equal to the parasitic resistance R<SUB>L1 </SUB>thereof. Likewise, a second resistance R<SUB>2 </SUB>is disposed in series with the second inductor and is equal to the parasitic resistance R<SUB>L2 </SUB>thereof. The Q enhancement circuit further includes a first transistor Q<SUB>1 </SUB>and a second transistor Q<SUB>2</SUB>. |
