PARALLEL ARCHITECTURE FOR MATRIX TRANSPOSITION

摘要

An extension to current multiple memory bank (309) video processing architecture is presented. A more powerful memory controller (310, 311) is incorporated, allowing computation of multiple memory addresses at both the input and the output data paths (316) making possible new combinations of reads and writes at the input and output ports. Matrix transposition computations required by the algorithms used in image and video processing are implemented in MAC modules and memory banks. The technique described here can be applied to other parallel processors including future VLIW DSP processors.