| 摘要 |
The present invention proposes a signal processor for Fast Fourier Transformation, FFT, of M<SUB>R</SUB>, M<SUB>R</SUB>>1, input data streams of 2<SUP>k </SUP>samples each, supplied in parallel. After multiplexing the input data streams in an interlaced manner, the resulting stream is subjected to FFT. The FFT device has a pipeline architecture composed of k stages with a respective feedback path including a single delay element per each stage of the pipeline architecture. The delay element and timing signals are adapted to cope with FFT processing of the multiplexed streams using the single FFT device only. After processing, the FFT processed data stream is demultiplexed. The present invention also concerns a corresponding signal processing method.
|
