APPARATUS AND METHOD FOR CONTROLLING CLOCK IN SEMICONDUCTOR MEMORY APPARATUS

摘要

An apparatus and a method for controlling a clock in a semiconductor integrated circuit are provided to shorten time required in delay locking operation of a clock. A control signal generation unit(10) defines initial operation by receiving a reference clock and a DLL(Delay Locked Loop) enable signal. A DLL circuit(20) generates a delay clock by delaying the reference clock in response to a course delay signal according to the initial operation, and generates a feedback clock by delaying the delay clock. A switching unit(30) passes the delay clock or the reference clock and the feedback clock according to the initial operation. A duty cycle correction unit(40) generates the course delay signal in response to a clock transferred from the switching unit, and generates an output clock by controlling duty ratio of the delay clock.