| 摘要 |
A memory cell array of a semiconductor memory device is provided to prevent electric interference between a storage node contact plug and a dummy word line by forming a number of dummy bit lines to have openings in an isolated mesh structure. A memory cell array of a semiconductor memory device comprises a main bit line, a main word line, a dummy bit line(dBL), a dummy word line(dWL), a landing plug(LP), a storage node contact plug. The main word line is formed perpendicularly to the main bit line. The dummy bit line is provided with a plurality of openings in an isolated mesh structure in parallel to the main bit line. The dummy word line crosses the dummy bit line. The landing plug is formed between dummy word lines to be opposed to at least one of the openings. The storage node contact plug is divided by the dummy bit line and contacts with the landing plug.
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