发明名称 Method of fabricating wafer level package
摘要 A method of fabricating wafer level package is provided. First, a wafer having a front and a rear surfaces is provided. Several fosses are then formed on the front surface of the wafer. Next, an insulative layer is formed on a surface of each fosse; a conductive layer is then formed on part of the front surface of the wafer and the insulative layer of each fosse. A solder layer is formed on the conductive layer above each fosse. Afterward, a first substrate is attached to the front surface. Several holes are formed on the rear surface, and the holes baring the solder layer are positioned corresponding to the fosses. Then, a second substrate is attached to the rear surface of the wafer. The second substrate has several conductive pillars correspondingly inserted into the holes for connecting the solder layers. Next, the conductive structures are formed on the second substrate.
申请公布号 US7435621(B2) 申请公布日期 2008.10.14
申请号 US20060416078 申请日期 2006.05.03
申请人 ADVANCED SEMICONDUCTOR ENGINEERING, INC. 发明人 YANG KUO-PIN
分类号 H01L21/00 主分类号 H01L21/00
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