发明名称 |
Decision feedback equalizer and clock and data recovery circuit for high speed applications |
摘要 |
A method for communicating data includes equalizing received data to reduce channel related distortion in the received data. A clock having frequency and/or phase fixed relative to the equalized data is extracted from the equalized data. The extracted clock is used to clock a retimer to generate recovered data.
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申请公布号 |
US7436882(B2) |
申请公布日期 |
2008.10.14 |
申请号 |
US20040774965 |
申请日期 |
2004.02.09 |
申请人 |
BROADCOM CORPORATION |
发明人 |
MOMTAZ AFSHIN |
分类号 |
H03H7/30;H03D3/24;H03K5/159;H04B10/18;H04L7/02;H04L7/033;H04L25/03 |
主分类号 |
H03H7/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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