| 摘要 |
A method for simulating timing in gate-level is provided to shorten entire debugging time. An RTL(Register Transfer Level) matched in cycle unit with a GL(Gate Level) model having a precise delay model reflecting layout and wiring results is generated by adding delay values, which are calculated from precise delay value for more than one signals among all signals of the GL model, to more than one signals of the matched RTL model in an original RTL model. The original RTL model is made from the GL model through manual processing and/or logical composition. GL timing simulation is performed in a time-parallel mode by slicing entire GL timing simulation time using the GL model based on status information of the RTL model or more than one design object of the RTL model, or input information and the status information. The status information is an RTL simulation result using the RTL model matched with the GL model in the cycle unit.
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