| 摘要 |
A method, system and computer program product for diagnosing a bridging defect in an integrated circuit including multiple nodes (20) are disclosed. Quiescent power supply current (IDDQ) of the integrated circuit (IC) is measured (40) under multiple test vectors (30). Logic states of the nodes on the IC are also obtained (20) under the multiple test vectors (30). The nodes are partitioned (S3) into sets based on their logic states under low-current test vectors. Large sets are further divided into subsets ("state-count subsets") (S 5-1) based on the logic states of nodes under high-current test vectors. For large sets, explicit evaluation under the IDDQ bridge fault model is performed only on pairs of nodes belonging to subsets having complementary state counts (S5-2, S5-3), to save system resources in computation. Exhaustive diagnosis considering all pairs of nodes on the IC is thus feasibly achieved due to the saving of system resources. |
