| 摘要 |
<p>An interface unit (1) is provided for use with a JTAG test and debug procedure involving a plurality of processor cores (11, 12, IN). The interface unit is provided with a logic unit that can translate test and debug commands into control signals. The control signals are applied to a power state machine coupled to a processor/core. The state of the power state machine can thereby be controlled and therefore the parameters of the associated processor/core, i.e., the power and clock parameters of the processor/core. In addition, the logic unit can generate control signals for activating switches, switches that controllably selective apply the TRST signal and the TMS signal to the TAP unit (111, 121, INl) of the processor /core. This capability permits the TAP units of each processor/core to be synchronized.</p> |
