发明名称 |
Method of testing a semiconductor integrated circuit |
摘要 |
A method of testing a semiconductor integrated circuit is disclosed. Specifically, a method of testing a semiconductor integrated circuit comprising a plurality of flip-flops is provided. The disclosed method includes connecting the plurality of flip-flops in series so that the plurality of flip-flops forms a scan-chain; inputting data to the scan-chain while supplying a clock signal to the plurality of flip-flops so that the data is set in the plurality of flip-flops; retaining the data in the plurality of flip-flops while inhibiting the clock signal for a predetermined period; restarting the clock signal to the plurality of flip-flops so that the data retained in the plurality of flip-flops is output from the scan-chain; and comparing the data output from the scan-chain and the data input to the scan-chain to test data retention of the plurality of flip-flops.
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申请公布号 |
US2008246503(A1) |
申请公布日期 |
2008.10.09 |
申请号 |
US20080078699 |
申请日期 |
2008.04.03 |
申请人 |
KAWASAKI MICROELECTRONICS, INC. |
发明人 |
SUMIDA SAKURAKO;SHIROKANE AKIO |
分类号 |
G01R31/302 |
主分类号 |
G01R31/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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