发明名称 MEMORY DATA INVERSION ARCHITECTURE FOR MINIMIZING POWER CONSUMPTION
摘要 A method for conserving power in a device is disclosed. The method generally includes the steps of (A) storing a plurality of data items in a plurality of bit cells in the device such that a majority of the bit cells holding the data items have a first logic state, wherein reading one of the bit cells having the first logic state consumes less power than reading one of the bit cells having a second logic state; (B) generating a polarity signal by analyzing the data items, the polarity signal indicating that the data items are stored in one of (i) an inverted condition and (ii) a non-inverted condition relative to a normal condition; and (C) driving at least one of the data items onto an external interface of the device in the normal condition during a read operation based on the polarity signal.
申请公布号 US2008247257(A1) 申请公布日期 2008.10.09
申请号 US20070696870 申请日期 2007.04.05
申请人 BROWN JEFFREY S 发明人 BROWN JEFFREY S.
分类号 G11C5/14 主分类号 G11C5/14
代理机构 代理人
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