| 摘要 |
PROBLEM TO BE SOLVED: To provide a Viterbi decoder in which power consumption can be easily increased and decreased according to requested decoding performance and circuit scale an be reduced. SOLUTION: A digital signal on which the Viterbi decoder performs decoding processing is a digital signal sequence to which the number of soft decision bits within a predetermined range is allocated. A branch metric arithmetic means includes: a serial arithmetic processing section which sequentially performs mathematical operation of a multi-bit digital signal; and a control section which adjusts the number of operation cycles thereof according to the bit width of the digital signal sequence, and the branch metric arithmetic means inputs the digital signal sequence to calculate a branch metric value. A state metric arithmetic means includes a serial arithmetic processing section which sequentially performs mathematical operation of the multi-bit digital signal and a control section which adjusts the number of operation cycles thereof in accordance with the bit width of the digital signal sequence, and inputs the branch metric value to calculate a state metric value. COPYRIGHT: (C)2009,JPO&INPIT
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