发明名称 PROCESS FOR MANUFACTURING VOLTAGE-CONTROLLED TRANSISTOR
摘要 The present invention provides a self-driven LDMOS which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal is clipped at a drain-voltage potential at said drain terminal. Since the gate-voltage potential is designed to be equal to or higher than a start-threshold voltage, the LDMOS is turned on accordingly. Besides, no additional die space and masking process are needed to manufacture the parasitic resistor. Furthermore, the parasitic resistor of the present invention does not lower the breakdown voltage and the operating speed of the LDMOS. In addition, when the two depletion boundaries pinch off, the gate-voltage potential does not vary in response to an increment of the drain-voltage potential.
申请公布号 US2008248638(A1) 申请公布日期 2008.10.09
申请号 US20080132605 申请日期 2008.06.03
申请人 SYSTEM GENERAL CORP. 发明人 CHIANG CHIU-CHIH;HUANG CHIH-FENG
分类号 H01L21/22 主分类号 H01L21/22
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