发明名称 Cache control method, cache device, and microcomputer
摘要 when a non-subsequent read occurs which is a read from a non-subsequent address not consecutive to the previous read address, a first cache memory sequentially caches respective data of the non-subsequent address and n addresses following the non-subsequent address, where n is an integer of one or greater, while the cached data of the n addresses are stored into a second cache memory, and subsequently, until the next non-subsequent read is performed, data of addresses following the last one of the n addresses are sequentially read from a memory, not via the first cache memory and stored into the second cache memory. In response to subsequent reads following the non-subsequent read, the second cache memory outputs the data of read addresses specified by the subsequent reads.
申请公布号 US2008250211(A1) 申请公布日期 2008.10.09
申请号 US20080076784 申请日期 2008.03.24
申请人 C/O NEC ELECTRONICS CORPORATION 发明人 IMAMIZU JUNICHI
分类号 G06F12/00 主分类号 G06F12/00
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