| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To achieve an increase in the capacitance of a capacitance element and reduce an area of a semiconductor device simultaneously. <P>SOLUTION: A plurality of capacitance elements whose types are different from one another are stacked on a semiconductor substrate 1, and connected in parallel with each other. These capacitance elements are arranged in the same plane area, and have plane dimensions almost identical with one another. Each capacitance element on the underside is allowed to serve as an MOS capacitance element C1 having an electrode of an n-type semiconductor region 4 formed on the semiconductor substrate 1 and the other electrode of an upper electrode 6 formed on the n-type semiconductor region 4 via an insulating film 5. MIM (Metal Insulator Metal) capacitance elements formed by comblike patterns of wiring M2 to M6 are arranged on the upper part of the capacitance element C1, and connected in parallel with the capacitance element C1. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
