发明名称 METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
申请公布号 US2008237752(A1) 申请公布日期 2008.10.02
申请号 US20080128796 申请日期 2008.05.29
申请人 发明人 KUJIRAI HIROSHI;OKUYAMA KOUSUKE;HATA KAZUHIRO;OYU KIYONORI;NAGAI RYO;UCHIYAMA HIROYUKI;KUMAUCHI TAKAHIRO;ICHISE TERUHISA
分类号 H01L21/768;H01L49/00;H01L21/28;H01L21/60;H01L21/8242;H01L27/092;H01L27/108;H01L29/49;H01L29/78 主分类号 H01L21/768
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