| 摘要 |
PURPOSE:To reduce the area for access of main memory of each processor unit set in a common bus address space regardless of the capacity of the main memory, by providing an address conversion memory to each processor unit. CONSTITUTION:When a processor (Pro)41 of a processor unit (ProU)1a gives access to a main memory in a unit ProU1d, the Pro4a is connected to a common bus 2 owing to a fact that a buffer gate 22a becomes enable and outputs an address indicating a window area for access of the main memory onto the bus 2. The units ProU1b-1d compare high-order 4 bits of a common bus address with the contents of registers 25b-25d through common bus address comparators 24b-24d. In this case, however, coincidence is secured with the comparator 24d. At the same time, 8 bits (19-12) of the common bus address received by the ProU1d are given to an address conversion memory 27d and the page information is outputted. This page information and all 12 bits (11-0) of the common bus address are given to a main memory 6d. |
