| 摘要 |
PURPOSE:To avoid delay of an output signal at the charge side despite an open type of a data output terminal by using a precharge means that charges previously a data bus before output of data in a memory read mode. CONSTITUTION:A data bus control signal DBC is set at 0 together with a column address strobe signal CAS set at 1, a write enable signal WE set at 0 and an output enable signal OE set at 0 respectively. Thus a signal PCG is set at 1 and an AND gate AN1 delivers 1 to supply it to the gate of a field effect transistor TR2. Then the TR2 is turned on and charging action is started to a data bus IOi via a resistance R1 and the TR2. This charging action is carried out quickly since a time constant obtained from the R1 and the stray capacity of a data bus is small. When the charging action is through, the signal OE is set at 1 and the read-out data are delivered onto the bus IOi. |
