| 摘要 |
A common-signal-terminal extracting section extracts common signal terminals from a netlist of the semiconductor device. An information converting section replaces the information of circuit components connected to the extracted common signal terminals by electric property information with reference a circuit-component library. A conformity detecting section determines whether or not the electric property information meets an electrical constraint rule with reference to an electrical constraint rule of the common signal terminals. An unverified-netlist creating section creates an unverified netlist from the netlist after excluding information of the common signal terminals. A simulation executing section executes logical simulation based on the created unverified netlist.
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