| 摘要 |
<p>A synchronous PCM digital transmission system including multilevel multiplexing wherein the higher order multiplexers interleave two or more tributary signals each of which comprises a multiplexed plurality of subtributaries. Multiplexer framing is achieved by means of an auxiliary frame pattern or byte, FT, which is slidable within the subscriber-defined frames. Each multiplexer in the system re-frames or slides FT and its associated overhead so that the FT bytes at each multiplexer are synchronized. The FT bytes can be used to frame or synchronize scrambling and de-scrambling circuitry. This concept provides multiplexer framing and yields high-speed multiplexed signals which are all exact multiples of the system clock rate, using relatively simple circuitry compared to competitive designs.</p> |
