| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To solve the problem wherein in a delay signal generating circuit successively loading delay data in a plurality of counters, down-counting the counters with the use of a reference clock, validating the outputs of the counters at timing, when the count values reaches a prescribed value and synthesizing the counter outputs thereby generating a delay signal, the number of registers is increased, since the number of counters has to be increased in order to increase the upper limit of delay data for continuously giving a delay trigger signal. <P>SOLUTION: A number-of-steps-variable shift register in which the number of steps is varied, by the delay data is used to shift the outputs of the counters by the shift register. When the upper limit of the delay data capable of continuously giving the delay trigger signal is to be increased, increase in the registers is significantly suppressed, as compared with a conventional manner. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
