| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an information processor capable of reducing the degradation of an access speed to a DRAM while encrypting an address. <P>SOLUTION: This information processor is provided with: a low address conversion part 5 for converting address signals A15 to A24 as the section showing a low address in an address output from a CPU 2 into a low address signal RA; and a column address conversion part 6 for converting the address signals A5 to A14 as a section showing a column address in the address output from the CPU 2 into a column address signal CA. Also, the information processor is provided with a DRAM controller 7 for performing access to a DRAM 8 by designating the low address signal RA and the column address signal CA, and for, when access to the memory address whose low address signal RA is the same is continuously performed more than once, not designating the low address signal RA in the second and following access. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
