| 摘要 |
PROBLEM TO BE SOLVED: To provide a cache control circuit for controlling a cache capacity to a proper size with respect to the state of a current application. SOLUTION: A cache control circuit for controlling a cache memory in a set associative system including a plurality of ways is provided with a measurement part for calculating a filling state corresponding to the ratio of the occupancy of valid data to the plurality of ways of the cache memory, an activity ratio corresponding to the access frequency of a cache memory and a mistake ratio corresponding to the ratio of the mistake of access to the cache memory; and a control part for controlling the start and stop of each of the plurality of ways of the cache memory according to the filling state, the activity ratio, and the mistake ratio. COPYRIGHT: (C)2009,JPO&INPIT
|
