发明名称 Prognosis of faults in electronic circuits
摘要 A process for a prognosis of faults in electronic circuits identifies parameters of a circuit under test. An upper and a lower limit is determined for one or more components of the circuit under test. A population of faulty and non-faulty circuits are generated for the circuit under test, and feature vectors are generated for each faulty and non-faulty circuit. The feature vectors are stored in a fault dictionary, and a feature vector for an implementation of the circuit under test in a field operation is generated. The feature vector for the implementation of the circuit under test in the field operation is compared to the feature vectors in the fault dictionary.
申请公布号 US2008244326(A1) 申请公布日期 2008.10.02
申请号 US20070728775 申请日期 2007.03.27
申请人 HONEYWELL INTERNATIONAL, INC. 发明人 BASU SUMIT K.
分类号 G06F11/00 主分类号 G06F11/00
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