| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To increase-speed of access to a memory cell array in a NAND type flash memory with a floating gate structure. <P>SOLUTION: For example, a row decoder 20 is arranged on one side of the memory cell array 10. A row decoder 30 for word lines is arranged on the other side of the memory cell array 10 so as to face the row decoder 20. In this way, word lines WL 0 to 31 of the memory cell array 10 are driven simultaneously by the row decoder 20 and the row decoder 30 for word lines. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
