发明名称 |
STRUCTURE FOR ONE-SAMPLE-PER-BIT DECISION FEEDBACK EQUALIZER (DFE) CLOCK AND DATA RECOVERY |
摘要 |
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER) is provided. The design generally includes a receiver circuit. The receiver circuit generally includes a decision feedback equalizer (DFE) that produces one sample per bit, and means for automatically self-adjusting the DFE to enable an eye centering process by which peak energy is maintained within the receiver circuit when phase error is a minimum.
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申请公布号 |
US2008240224(A1) |
申请公布日期 |
2008.10.02 |
申请号 |
US20080138214 |
申请日期 |
2008.06.12 |
申请人 |
CARBALLO JUAN A;CRANFORD HAYDEN C;NICHOLLS GARETH J;NORMAN VERNON R;SCHMATZ MARTIN L |
发明人 |
CARBALLO JUAN A.;CRANFORD HAYDEN C.;NICHOLLS GARETH J.;NORMAN VERNON R.;SCHMATZ MARTIN L. |
分类号 |
H04L27/01 |
主分类号 |
H04L27/01 |
代理机构 |
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